An Efficient Constant Multiplier Architecture for Reconfigurable Fir Filter Synthesis

This paper proposes a reconfigurable finite impulse response (FIR) filter using constant multiplier algorithm with applying pipeline technique. To design a high performance Reconfigurable fir filter, according to the proposed constant multiplier algorithm with Retiming pipelining method has been applied in co-efficient generator block. This method capable of reducing the switching activity of constant multiplier process by 28% as compared to that of existing method. In this technique area and delay can be reduced approximately 24% and 62% respectively compare to previous method. This reconfigurable fir filter can be designed using Verilog hardware Description Language (HDL) and its behaviour can be tested using Modelsim 6.3c software and synthesized in Xilinx10.1.